1. Field of the Invention
This invention relates to complementary field effect transistors fabricated as integrated circuits.
2. Description of the Prior Art
The applications of CMOS type circuits in low power and relatively low speed systems such as calculators, portable data buffers, small computers, etc., are by now well known. Such devices have enjoyed considerable commercial success. However, where it has been desired to integrate such devices in highly dense fashion in a single semiconductor substrate, designers in the field have encountered a stumbling block which has not been overcome heretofore.
In the conventional structure, an N channel device is formed in a P region and a P channel device is formed in an N region adjacent said P region. P type contacts are made in the P region and N type contacts are made in the P region in the area between the active N and P channel devices. Such a structure is shown, for example, in U.S. Pat. No. 3,712,995 in the name of G. W. Steudel. In highly dense circuits where such devices are separated by no more than the few microns, a four-region PNPN structure is thereby formed. Under normal operating conditions as an FET circuit, this structure may function as a silicon-controlled rectifier (SCR) which, under some circumstances, becomes latched and remains so. This results in a malfunction of the field effect transistors, rendering the circuits inoperative.
Heretofore, semiconductor designers have avoided this problem in commercial intergrated circuits by spacing the field effect transistors far enough apart within the chip so that parasitic circuits are negligible. However, such low circuit densities make the CMOS family of circuits less desirable than other competitive technologies such as bipolar and single channel integrated circuit field effect transistors. Other devices are commercially available in which the problem has not been solved. Careful control of the input and power supply potentials is required to avoid latchup in such devices.
The parasitic problem is now recognized as the principal factor which has limited the packing density of CMOS devices. It overshadows the limitations previously associated with integrated circuit techniques -- excessive heat dissipation and the inability during fabrication to accurately define the individual regions within the semiconductor chip.